The present invention relates to a bus arbitration means mounted in various information processors such as a personal computer and work station and more particularly to a means for performing suitable arbitration by improving the bus access efficiency when accesses to an I/O device and a storage compete each other.
As a bus installed in various conventional information processors which is a high-speed system bus in view of multi-processor control, for example, the so-called "Future bus+" described in "IEEE Draft Standard P896. 1R/D8.5: Future bus+ Logical Layer Specifications, IEEE Computer Society Press (1991) PP 63-104" has been proposed.
With respect to a high-speed information processor such as a server comprising a personal computer or work station, there are many processors having a structure using a high-speed system bus represented by such Future bus+. To such a system bus, a plurality of modules, for example, a plurality of processors, a processor interface, a main storage, an I/O device, and others are connected. With respect to an I/O device, a constitution that the I/O device is connected to a system bus via a converter for performing protocol conversion of information on the system bus to information on an I/O bus and the I/O bus is often proposed.
Recently, however, in the field of information processors, as the system clock frequency to be supplied to a processor increases suddenly, it is becoming one of the greatest factors for deciding the system performance whether the data access speed to a processor and main storage can be increased in correspondence with high performance of the processor.
In such a system, a constitution that a bus for connecting a processor and main storage and an I/O bus for connecting an I/O device are individually installed via a bus converter (bus adapter), that is, the so-called hierarchy of buses has advanced in view of compatibility with an existing I/O device, multi-line connection, and connection to various I/O devices.
Therefore, it is important to develop a bus control means for performing various conversion processes between buses efficiently. Furthermore, an art of bus control for realizing a higher throughput is, for example, disclosed in Japanese Laid-Open Patent Application Number 5-324544. In these buses, to realize a high throughput, use of a method that a buffer for transaction reception is provided beforehand in the module on the bus slave (hereinafter referred to as just "slave" properly) side without performing handshaking in each cycle and data is continuously written into the buffer installed in the slave on the receiving side after the bus master obtains a bus access right has been proposed.